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/content/aip/journal/apl/107/20/10.1063/1.4935985
2015-11-16
2016-12-07

Abstract

Research on graphene field-effect transistors (GFETs) has mainly relied on devices fabricated using electron-beam lithography for pattern generation, a method that has known problems with polymer contaminants. GFETs fabricated via photo-lithography suffer even worse from other chemical contaminations, which may lead to strong unintentional doping of the graphene. In this letter, we report on a scalable fabrication process for reliable GFETs based on ordinary photo-lithography by eliminating the aforementioned issues. The key to making this GFET processing compatible with silicon technology lies in a two-in-one process where a gate dielectric is deposited by means of atomic layer deposition. During this deposition step, contaminants, likely unintentionally introduced during the graphene transfer and patterning, are effectively removed. The resulting GFETs exhibit current-voltage characteristics representative to that of intrinsic non-doped graphene. Fundamental aspects pertaining to the surface engineering employed in this work are investigated in the light of chemical analysis in combination with electrical characterization.

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