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Reduction in crystallographic surface defects and strain in 0.2‐μm‐thick silicon‐on‐sapphire films by repetitive implantation and solid‐phase epitaxy
1.S. S. Lau, S. Matteson, J. W. Mayer, P. Revesz, J. Gyulai, J. Roth, T. W. Sigrnon, and T. Cass, Appl. Phys. Lett. 34, 76 (1979).
2.I. Golecki and M.‐A. Nicolet, Solid State Electron. 23, 803 (1980).
3.I. Golecki, G. Kinoshita, and B. M. Paine, Nucl. Instrum. Methods 182/183, 675 (1981).
4.T. Inoue and T. Yoshii, Appl. Phys. Lett. 36, 64 (1980).
5.M. E. Roulet, P. Schwob, I. Golecki, and M.‐A. Nicolet, Electron. Lett. 15, 527 (1979).
6.An additional, low‐dose implant (85 keV, ) was also performed in order to study its effects on the electrical properties of the Si film. This implant is not, however, an integral or necessary part of the recrystallization technique, and does not alter the main conclusions of this study.
7.The oxygen introduced in the Si film is expected to slow the SPEG somewhat near the sapphire interface, but this is not an essential part of this study;
7.see E. F. Kennedy, L. Csepregi, J. W. Mayer, and T. W. Sigmon, J. Appl. Phys. 48, 4241 (1977).
8.This shallow Si implant was designed for a ‐thick Si film, but due to lateral variations in film thickness, the Si film was only thick in the implanted area. It was shown in a previous study1 that a region containing extended defects (possibly dislocations) is formed between the amorphized and the single‐crystal regions following furnace annealing of such RT implants. Thus because the energy of the Si ions was too high for the actual thickness of the film, the extent of this defective region might have reached the sapphire interface. TEM measurements are needed to draw more definitive conclusions.
9.I. Golecki, H. L. Glass, G. Kinoshita, and T. J. Magee, Appl. Surf. Sci. (in press).
10.G. A. Sai‐Halasz, F. F. Fang, T. O. Sedgwick, and A. Segmüller, Appl. Phys. Lett. 36, 419 (1980).
11.I. Golecki (unpublished);
11.e.g., an 80‐keV, RT implant into a ‐thick CVD SOS film, followed by a furnace annealing of 98 min at 565 °C, lowered the value from 0.091 to 0.076 and the average value in the top region of the Si film from to
12.Y. Quéré, J. Nucl. Mater. 53, 262 (1974);
12.Y. Quéré, Rad. Eff. 28, 253 (1976).
13.While our work was in progress, a similar SOS improvement method was reported by T. Yoshii (Electronic Materials Conference, Santa Barbara, CA, June 1981, unpublished). Starting with a ‐thick CVD SOS film, an improvement of 35% was obtained in the FET electron mobility of an n‐channel MOS transistor. Chemical staining showed a reduction of 100 in the density of crystalline defects throughout the thickness of the Si film. These results, which were obtained using characterization techniques complementary to the ion channeling and x‐ray diffraction methods used in our work, are in agreement with ours. However, our process uses an annealing temperature on the order of 560 °C, whereas T. Yoshii’s required a temperature of 1000 °C, which is higher than the typical 930°C deposition temperature in CVD of Si‐on‐sapphire.
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