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Minimization of the offset voltage in heterojunction dipolar transistors by using a thick spacer
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10.1063/1.109104
/content/aip/journal/apl/62/24/10.1063/1.109104
http://aip.metastore.ingenta.com/content/aip/journal/apl/62/24/10.1063/1.109104
/content/aip/journal/apl/62/24/10.1063/1.109104
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/content/aip/journal/apl/62/24/10.1063/1.109104
1993-06-14
2014-11-26
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Minimization of the offset voltage in heterojunction dipolar transistors by using a thick spacer
http://aip.metastore.ingenta.com/content/aip/journal/apl/62/24/10.1063/1.109104
10.1063/1.109104
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