(a) Schematic view of in-plane-gated FET (IPGFET). Au electrode is formed by e-beam lithography and potassium iodide (KI) etching. The gate insulating region and device isolation region, which were exposed to the oxygen plasma, yielded low gate leakage current. (b) AFM image of IPGFET. The channel width is approximately . The gate voltage is applied to two side-gate electrodes, and channel conductance is modulated from both sides. The insulating region has an approximately width between the gate electrode and channel.
Hysteresis behavior observed in the curve of the diamond IPGFETs at room temperature under light irradiation. The bias voltage . The threshold voltaqe is under the bias condition from 10 to , and under the bias condition from to . The threshold voltage shift of is observed upon sweeping the gate voltage along the points .
(a) Hysteresis characteristics under the relative radiant flux densities of 1.4, 0.7, and . Drain current is on the logarithmic scale. The ON–OFF ratio at is more than five orders of magnitude. The threshold voltage shifts to the more negative side under the bias condition from 10 to . (b) Hysteresis characteristics under the relative radiant flux densities of 1.4, 5.6, and . The threshold voltage shifts from at the radiant flux density of to at the radiant flux density of under the bias condition from to .
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