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(a) Current–voltage characteristic of Y-junction CNTs. The top inset is a schematic of the Y-junction array membrane and the “sandwich” configuration used to apply positive bias to the top contact relative to the bottom. The bottom inset is a AFM topography of an individual Y-junction. (b) Differential conductance of Y-junctions. The left inset shows a log–log plot of the zero-bias conductance vs temperature for both Y junctions and straight CNTs (scaled down for comparison). The sloped line indicates power-law behavior , with as shown. The Y-junction conductance is seen to level off for low-temperatures (horizontal line as a guide). The right inset shows the differential conductance of the straight CNTs for various temperatures. The number of tubes contacted in these plots was similar but not identical.
Double logarithmic plot of Y-junction differential conductance vs voltage for (a) positive bias and (b) negative bias. At high voltages a power-law dependence, , is seen as indicated by the solid lines. The small vertical offset between curves at high bias is likely caused by changes in carrier properties away from the branching region unrelated to the junction effect [see Fig. 3(b)].
(a) Diagram of Y-junction CNT geometry. The lack of inversion symmetry is indicated schematically by the arrows for different parts of the Y junction. (b) Ratio of Y-junction conductance , for various temperatures. The straight line is a guide.
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