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Voltage-induced degradation in self-aligned polycrystalline silicon gate -type field-effect transistors with gate dielectrics
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10.1063/1.1834992
/content/aip/journal/apl/85/24/10.1063/1.1834992
http://aip.metastore.ingenta.com/content/aip/journal/apl/85/24/10.1063/1.1834992
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

HRTEM images of poly- gate dielectric∕Si channel structures in transistors: (a) , (b) , and (c) .

Image of FIG. 2.
FIG. 2.

(a) and (b) curves of the three samples at the fresh state (closed symbols) and after a voltage stress for (open symbols): Inset figures in (a) and (b) show the variations in as a function of and as a function of of three samples, respectively.

Image of FIG. 3.
FIG. 3.

XPS spectra of of (a) , (b) , and (c) samples with peak deconvolution results. The peaks from the low binding energy belong to the Si substrate , , , , , and .

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/content/aip/journal/apl/85/24/10.1063/1.1834992
2004-12-09
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Voltage-induced degradation in self-aligned polycrystalline silicon gate n-type field-effect transistors with HfO2 gate dielectrics
http://aip.metastore.ingenta.com/content/aip/journal/apl/85/24/10.1063/1.1834992
10.1063/1.1834992
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