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Influence of buffer layer thickness on memory effects of structures
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10.1063/1.1771458
/content/aip/journal/apl/85/8/10.1063/1.1771458
http://aip.metastore.ingenta.com/content/aip/journal/apl/85/8/10.1063/1.1771458
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

memory window for (a) , with the counterclockwise hysterisis direction (ferroelectric polarization dominated) and (b) with the clockwise hysterisis direction (trapping related).

Image of FIG. 2.
FIG. 2.

memory window as a function of temperature for (a) and (b) .

Image of FIG. 3.
FIG. 3.

The band diagrams for the sample under various bias conditions, surface is (a) in accumulation, (b) still in accumulation, (c) in inversion, and (d) in either depletion or inversion.

Image of FIG. 4.
FIG. 4.

The band diagrams for the sample under various conditions, surface is (a) in accumulation, (b) carrier trapping at the positive gate bias, (c) depletion or inversion, and (d) carrier trapping in the negative bias.

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/content/aip/journal/apl/85/8/10.1063/1.1771458
2004-08-17
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Influence of buffer layer thickness on memory effects of SrBi2Ta2O9∕SiN∕Si structures
http://aip.metastore.ingenta.com/content/aip/journal/apl/85/8/10.1063/1.1771458
10.1063/1.1771458
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