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Effects of tantalum penetration through hafnium oxide layer on carrier generation rate in silicon substrate and carrier mobility degradation
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10.1063/1.1845588
/content/aip/journal/apl/86/1/10.1063/1.1845588
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/1/10.1063/1.1845588
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Figures

Image of FIG. 1.
FIG. 1.

transient and Zerbst plots with different gate electrode structure shows that bulk carrier generation rate was degraded for the TaN gate devices.

Image of FIG. 2.
FIG. 2.

SIMS analysis shows that Ta atoms were penetrated into Si-substrate. These penetrated Ta atoms induced bulk trap centers and led to shorter bulk carrier generation rate. XPS result shows that Ta atoms were incorporated in dielectric layer.

Image of FIG. 3.
FIG. 3.

vs EOT plot shows that Ta incorporation did not change the effective dielectric constant.

Image of FIG. 4.
FIG. 4.

Characteristics of the stress-induced flat-band voltage shift imply that Ta incorporation in devices seemed to induce higher pre-existing traps compared to that of poly-Si gate. For , however, there was no difference between TaN gate and poly-Si gate device. Inset figure represents that universal mobility and show that mobility degradation in TaN gate device was primarily caused by fixed charge and interface states of the high- dielectrics due to Ta incorporation.

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/content/aip/journal/apl/86/1/10.1063/1.1845588
2004-12-23
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effects of tantalum penetration through hafnium oxide layer on carrier generation rate in silicon substrate and carrier mobility degradation
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/1/10.1063/1.1845588
10.1063/1.1845588
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