1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors
Rent:
Rent this article for
USD
10.1063/1.1891289
/content/aip/journal/apl/86/12/10.1063/1.1891289
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/12/10.1063/1.1891289
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic process flow of vertical asymmetric DG MOSFET: (a) thicker vertical channel formation and dopant ion implantation for IBRE and S/D formation, (b) channel thinning by utilizing IBRE, (c) gate oxidation and activation and undoped poly-Si deposition, (d) asymmetric gate doping, (e) self-aligned DG formation by RIE, (f) interlayer dielectrics deposition and metallization. Because of the vertical configuration of our DG MOSFET, the self-aligned asymmetric DG is easily incorporated into the FET, using tilted ion implantation technology and RIE.

Image of FIG. 2.
FIG. 2.

(a) A schematic and (b) cross-sectional SEM image of the gate-length vertical asymmetric DG MOSFET .

Image of FIG. 3.
FIG. 3.

Measured characteristics for (a) symmetric DG MOSFET and (b) asymmetric DG MOSFET. As the channel thickness is reduced, the short-channel-effects are suppressed in both symmetric and asymmetric DG MOSFETs.

Image of FIG. 4.
FIG. 4.

Measured dependence of on for asymmetric and symmetric DG MOSFETs. Experimental results are in good agreement with both the value estimated using device simulation and also the analytically calculated value. Thanks to the asymmetric DG and the ultrathin channel, a positive of is obtained for -channel vertical DG MOSFETs.

Image of FIG. 5.
FIG. 5.

Measured dependence of the linear mode -slope (solid lines) and the saturation mode (dotted lines) on for the asymmetric and symmetric DG MOSFETs. A low -slope of . is achieved for the thinnest channel asymmetric DG MOSFET. Despite of a thick gate oxide of , the relatively large peak of and are achieved for the asymmetric and symmetric DG MOSFETs, respectively.

Loading

Article metrics loading...

/content/aip/journal/apl/86/12/10.1063/1.1891289
2005-03-18
2014-04-21
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/12/10.1063/1.1891289
10.1063/1.1891289
SEARCH_EXPAND_ITEM