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Schematic process flow of vertical asymmetric DG MOSFET: (a) thicker vertical channel formation and dopant ion implantation for IBRE and S/D formation, (b) channel thinning by utilizing IBRE, (c) gate oxidation and activation and undoped poly-Si deposition, (d) asymmetric gate doping, (e) self-aligned DG formation by RIE, (f) interlayer dielectrics deposition and metallization. Because of the vertical configuration of our DG MOSFET, the self-aligned asymmetric DG is easily incorporated into the FET, using tilted ion implantation technology and RIE.
(a) A schematic and (b) cross-sectional SEM image of the gate-length vertical asymmetric DG MOSFET .
Measured characteristics for (a) symmetric DG MOSFET and (b) asymmetric DG MOSFET. As the channel thickness is reduced, the short-channel-effects are suppressed in both symmetric and asymmetric DG MOSFETs.
Measured dependence of on for asymmetric and symmetric DG MOSFETs. Experimental results are in good agreement with both the value estimated using device simulation and also the analytically calculated value. Thanks to the asymmetric DG and the ultrathin channel, a positive of is obtained for -channel vertical DG MOSFETs.
Measured dependence of the linear mode -slope (solid lines) and the saturation mode (dotted lines) on for the asymmetric and symmetric DG MOSFETs. A low -slope of . is achieved for the thinnest channel asymmetric DG MOSFET. Despite of a thick gate oxide of , the relatively large peak of and are achieved for the asymmetric and symmetric DG MOSFETs, respectively.
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