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Schematic of Si channel transistor with stressors in source and drain regions. The inset illustrates the crystal lattices in the vicinity of the vertical and horizontal heterojunctions, with arrows indicating the nature of the stresses experienced by the crystal lattices. At the vertical heterojunction, the silicon region has a vertical tensile strain component, and at the horizontal heterojunction, the silicon region immediately underlying the stressor has a horizontal tensile strain component. The axis divides the transistor structure into two halves, and the axis runs along the substrate surface. A nonuniform grid was chosen such that the grid size is fine in the vicinity of the heterojunctions and channel region where the strain gradient is large, but larger at locations far away from the stressors.
Profiles of (a) the lateral strain component and (b) the vertical strain component in the transistor structure, showing the channel region and the stressors. The interstressor spacing is . The interface between Si and SiGe is indicated by dashed lines. Tensile strain is positive, and compressive strain is negative.
Profile of lateral strain component (a) along a vertical line from the surface of the drain region to the silicon substrate at , and (b) along a horizontal line from the source to the drain at a depth of below the channel surface.
Lateral and vertical strain components, and , respectively, in the top of the transistor channel plotted as a function of (a) the Ge mole fraction in the stressor and (b) the spacing between the source stressor and the drain stressor. The solid symbols plot the spatial average of each strain component over the region defined by and . The bars indicate the maximum and minimum strain magnitudes observed in the above mentioned region.
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