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curves for the three Ni thicknesses (10, 20 and 30 nm) for 3 nm . Gradual shift in as a result of increasing Ni thickness can be noted.
(a) vs EOT for the Ni∕Si samples. Good fit of the thicker Ni samples as against that for thinnest Ni sample can be noted. (b) Gains in EOT is maximum for the thinnest Ni∕Si sample.
(a) Auger depth profiling, (b) HRTEM image, and (c) XRD data plot for 50 nm W∕20 nm Ni∕20 nm Si∕3 nm showing presence of nickel-rich silicon and nickel monosilicide after 400 °C forming gas anneal.
(a) characteristics of the Ni∕Si stacks. Inset: Comparison with the theory of the 20 nm∕20 nm Ni∕Si stack for the thinnest dielectric. (b) Leakage current comparison for the Ni∕Si stacks at different temperatures for the thinnest dielectric. Low leakage indicates dielectric integrity is maintained at 700 °C.
(a) Auger depth profiling and (b) HRTEM for 50 nm W∕20 nm Mo∕20 nm Si∕3 nm stack with region , region 2—unreacted moly, region , region 4—unreacted Si.
Work function values of the Ni∕Si stacks at different temperatures.
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