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Reversible and irreversible trapping at room temperature in poly(thiophene) thin-film transistors
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10.1063/1.1968437
/content/aip/journal/apl/86/26/10.1063/1.1968437
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/26/10.1063/1.1968437
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Normalized current as a function of time for different dc stress times (a). Ratio of released charge to total trapped charge as a function of dc stress time (inset). Partition of trapped charge between reversibly and irreversibly trapped charge as a function of gate voltage after stressing the devices for (b).

Image of FIG. 2.
FIG. 2.

shift calculated according to Eq. (1) as a function of time for different pulse lengths and duty cycles (a). The time units are defined as follows. For , the abscissa is the gate on-time, for , the abscissa is the real time. shift measured with low duty cycle biasing as a function of gate-on time for different gate voltages (b). For all the curves shown in the figure, the recovery measured after the biasing cycle was . The parameters used to fit the curves to Eq. (2) were , , and , and was extracted from transfer measurements prior to stressing the device. varied between 4 and .

Image of FIG. 3.
FIG. 3.

as a function of according to Eq. (5). The parameters used to calculate were extracted from the fit of the curve of Fig. 2(b) and are as follows: , , , and .

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/content/aip/journal/apl/86/26/10.1063/1.1968437
2005-06-23
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Reversible and irreversible trapping at room temperature in poly(thiophene) thin-film transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/26/10.1063/1.1968437
10.1063/1.1968437
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