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Nanometer-scale two-terminal semiconductor memory operating at room temperature
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10.1063/1.1852711
/content/aip/journal/apl/86/4/10.1063/1.1852711
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/4/10.1063/1.1852711
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) An atomic force micrograph of a typical SSM device consisting of two etched trenches. Also schematically shown are the two bias contacts.

Image of FIG. 2.
FIG. 2.

(a) characteristics of a typical SSM measured at . (b) Experimental results of the memory effect, performed with test pulses at −0.5 V, and state-switching voltages of ±1 V. After each pulse of +1 V, the current remains zero during test pulses of −0.5 V, corresponding to the memory state of 0. After each pulse of −1 V, the current becomes nonzero during test pulses, corresponding to the memory state of 1.

Image of FIG. 3.
FIG. 3.

Experimental results of the memory effect at room temperature, performed with test pulses of −0.5 V, and state-switching voltages of ±4 V.

Image of FIG. 4.
FIG. 4.

(Color online) (a) A sketch of an SSM. (b) The conduction-band profile along the dashed line in (a). (c) When the applied bias is beyond the negative threshold voltage, , the surface states will be discharged by charge transfer into the channel. The opposite process happens if the applied bias is beyond the positive threshold, (d).

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/content/aip/journal/apl/86/4/10.1063/1.1852711
2005-01-18
2014-04-21
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Nanometer-scale two-terminal semiconductor memory operating at room temperature
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/4/10.1063/1.1852711
10.1063/1.1852711
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