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Schematic drawing of a SGT structure used in simulations showing the spreading of the reverse biased source barrier depletion region towards the semiconductor-insulator interface.
Normalized transistor characteristic per unit width of experimental and simulated SGT devices.
Simulated SGT transistor characteristics for high current devices with three different source-drain separations.
The change in saturation voltage with gate voltage for SGTs with a range of source-drain separation (a) experimental and (b) simulated results .
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