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Modeling of high-current source-gated transistors in amorphous silicon
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10.1063/1.1865348
/content/aip/journal/apl/86/7/10.1063/1.1865348
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/7/10.1063/1.1865348
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic drawing of a SGT structure used in simulations showing the spreading of the reverse biased source barrier depletion region towards the semiconductor-insulator interface.

Image of FIG. 2.
FIG. 2.

Normalized transistor characteristic per unit width of experimental and simulated SGT devices.

Image of FIG. 3.
FIG. 3.

Simulated SGT transistor characteristics for high current devices with three different source-drain separations.

Image of FIG. 4.
FIG. 4.

The change in saturation voltage with gate voltage for SGTs with a range of source-drain separation (a) experimental and (b) simulated results .

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/content/aip/journal/apl/86/7/10.1063/1.1865348
2005-02-08
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Modeling of high-current source-gated transistors in amorphous silicon
http://aip.metastore.ingenta.com/content/aip/journal/apl/86/7/10.1063/1.1865348
10.1063/1.1865348
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