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Schematic of transistor structures with epitaxially grown or in the S∕D regions to form S∕D stressors. The inset shows a HRTEM image of a structure with S∕D stressor. The gate electrode has a feature size of and the thickness of is . The pitch of the gate array pattern is .
A high magnification HRTEM image of a transistor structure with stressors in the S∕D region. The region enclosed by the dashed line features a material which was pseudomorphically grown on the recessed S∕D region.
(a) The reciprocal space diffractogram is obtained by FFT of a selected region in the transmission electron microscopy image of Fig. 2. The diffractogram is then filtered to obtain (b) the (002) reflection and (c) the (220) reflection, which contain information about the lattice spacings in the vertical and lateral directions, respectively. The intensity profile for the (002) reflection is shown in (d). The separation between the intensity peaks is twice the separation from to each peak, and can be translated into real space lattice spacing using .
The distribution of strain components in a transistor structure with stressors in the S∕D regions. (a) Large lateral compressive strain is observed near the heterojunction and directly beneath the surface. (b) The lattice is stretched in the vertical direction, and a vertical tensile strain is induced.
The distribution of (a) the lateral strain component and (b) the vertical strain component in a transistor structure with source∕drain stressors. A relatively large lateral tensile strain was induced in near the heterojunction. The magnitude of the lateral tensile strain decreases with increasing . The lattice also interacts with the lattice to induce a vertical compressive strain in the channel.
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