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(a) Schematic plot of PDMILC M10 poly-Si TFT with source, drain, gate, ten nanowire channels, contact holes, and MILC seeding window. The distance between the MILC seeding window edge and middle of active channel is . (b) Cross-sectional view of PDMILC TFT, which was a conventional MOSFET with offset structure.
(a) SEM photograph of active pattern with the source, the drain, ten nanowire channels, and MILC seeding window. The inset SEM photograph shows the each nanowire width of . (b) SEM photograph of poly-Si grain structure in active channel of S1 MILC poly-Si TFT following Secco solution etching. The average poly-Si lateral grain size is . The inset optical microscopy photograph depicts a MILC length of . (c) SEM photograph of grain structure in one of ten nanowire MILC poly-Si TFTs (M10) following Secco etching. The poly-Si lateral grain length is .
Transfer curves (left) and field-effect mobility (right) of a series of PDMILC TFT of a multichannel with various widths at the gate length of .
Field-effect mobility average and standard deviation vs the gate length, for a particular M10 TFT structure.
Devices dimension of S1, M2, M5, and M10 PDMILC poly-Si TFTs. All devices have the same active channel thickness of , gate TEOS-oxide thickness, of , and gate length of .
Device parameters average and standard deviation value of M10, M5, M2, and S1 TFTs with gate length of . The is defined as the gate voltage required to achieve a normalized drain current of at .
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