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The structure of the epitaxial layers, showing the position of the C-doped layer and the position of the junctions. An oxide/nitride mask was used to pattern the junctions. After junction formation, a three-step nickel silicidation (10 nm Ni) was used to decrease the contact resistance.
Reverse leakage current density vs voltage for strained junctions and a co-processed silicon reference sample, measured at room temperature. Decreasing the threading dislocation density linearly decreases the leakage. Area of the junctions is .
Inverse generation lifetime vs threading dislocation density. The data points are calculated from current and capacitance measurements at 25 mV reverse voltage. The line shows a linear fit through the data points.
Calculated leakage per dislocation vs reverse voltage for different working temperatures. The leakage was calculated, based on current measurements on the three substrates of Table I at different temperatures. A power law was used to model the leakage vs threading dislocation density, for every reverse voltage and temperature. For higher temperatures and reverse voltages, the dependence of current vs TDD becomes more and more sublinear, yielding a minimal fitted power of 0.75 at 125 °C and 2 V reverse bias.
Overview of the silicon–germanium virtual substrates of this experiment, showing the threading dislocation density, counted after defect etching, and the estimated minority carrier generation lifetime .
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