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Room-temperature semiconductor heterostructure refrigeration
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10.1063/1.1992651
/content/aip/journal/apl/87/2/10.1063/1.1992651
http://aip.metastore.ingenta.com/content/aip/journal/apl/87/2/10.1063/1.1992651
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

The upper part (A) illustrate the SHR structure and the corresponding potential profile under a bias voltage . The physical processes for the operation of this SHR are shown in the lower part (B). When a current flows under a bias voltage , the temperature in the region between the two thick alloy layers is lowered by an amount .

Image of FIG. 2.
FIG. 2.

Under an applied bias voltage , each curve represents the temperature drop of the inner part of the SHR for a given outer environment temperature .

Image of FIG. 3.
FIG. 3.

Similar results as in Fig. 2 but for a different device structure.

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/content/aip/journal/apl/87/2/10.1063/1.1992651
2005-07-08
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Room-temperature semiconductor heterostructure refrigeration
http://aip.metastore.ingenta.com/content/aip/journal/apl/87/2/10.1063/1.1992651
10.1063/1.1992651
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