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Multilevel charge storage in silicon nanocrystal multilayers
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10.1063/1.2132083
/content/aip/journal/apl/87/20/10.1063/1.2132083
http://aip.metastore.ingenta.com/content/aip/journal/apl/87/20/10.1063/1.2132083
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic image of the multilayer MOS structure, (b) TEM image of the realized structure with three layers of Si nanocrystals embedded in .

Image of FIG. 2.
FIG. 2.

High frequency characteristics of the sample (a) with two layers, and (b) with three layers. The widths of hysteresis gradually widen with increased the programming bias.

Image of FIG. 3.
FIG. 3.

The dependence of the memory window on programming voltage. There are three apparent stages observed for the three layer sample, and two stages for the two layer sample. Each stage is spaced by about .

Image of FIG. 4.
FIG. 4.

Retention characteristics of the three layer sample after charging at different writing biases.

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/content/aip/journal/apl/87/20/10.1063/1.2132083
2005-11-11
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Multilevel charge storage in silicon nanocrystal multilayers
http://aip.metastore.ingenta.com/content/aip/journal/apl/87/20/10.1063/1.2132083
10.1063/1.2132083
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