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(Color online) (a) Detailed process steps to obtain S-AFI-S or OS-US-OS junction. Step 1: Cuprate film grown on a substrate. Step 2: Si-overlayer deposited using lithography and lift-off; top view of the device after this step is shown in Fig. 2(a). Step 3: High temperature (450 °C) annealing in vacuum to reduce oxygen content in the entire film. Step 4: Low temperature (250 °C) annealing in ozone to oxidize outside Si-overlayered region. (b) An alternative procedure, which we have not used but is equally valid, to make the same final pattern. This second procedure is different from (a) only in steps 2 and 3 in that high temperature annealing to reduce oxygen is done before the overlayer is deposited. This procedure may be useful if the overlayer is not compatible with the high temperature process.
(Color online) Resistance vs temperature plots for S-AFI-S junctions at different stages. (a) Top view of the junction structure and the four point probe geometry. Si-overlayer of width is shown. (b) Before step 3 in Fig. 1(a), both junctions with and without a Si-overlayer are superconducting near 80 K. (c) After step 4, Si-overlayered region has become insulating, while the control junction without any Si-overlayer remains superconducting with almost the same as in (b). (d) After the sample is exposed to ozone at a high temperature, the insulating sample has become superconducting again with of 80 K. This verifies that the insulating behavior in (c) is due to oxygen deficiency and not due to sample damage.
Current vs electric field plot for S-AFI-S junctions. Note the severe nonlinearity. Straight lines at large electric field correspond to a power law dependence of . Electric field is defined as the voltage divided by the width of each Si overlayer. Curves of different widths do not overlap. This implies that the actual oxygen deficient linewidths are smaller than the overlayer widths due to nonzero oxygen diffusion length. This effect can be minimized by optimizing the oxidation temperature and time during step 4 in Fig. 1(a).
(Color online) Resistance vs temperature for OS-US-OS junctions; (a) and (b) differ only in the vertical axis format. For and , the transitions at the higher temperature (80 K) are from the outer conductors (OS) and the transitions at the lower temperature (40 K) are from the central region under the Si overlayer (US). For , only one transition occurs at the lower temperature because the resistance is dominated by the wide underdoped superconductor (US).
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