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Performance of a spin-based insulated gate field effect transistor
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10.1063/1.2192152
/content/aip/journal/apl/88/16/10.1063/1.2192152
http://aip.metastore.ingenta.com/content/aip/journal/apl/88/16/10.1063/1.2192152

Figures

Image of FIG. 1.
FIG. 1.

Schematic barriers used in (a) a MOSFET and (b) a spin-based FET. A MOSFET works by controlling the height of the barrier, with a barrier height and width largely determined by the desired on-off current ratio and leakage current. The spin-based FET considered here works by controlling the nature of the initial state moving past the barrier in (b); if the initial state is fully spin polarized the transistor is off, otherwise it is on.

Image of FIG. 2.
FIG. 2.

Spin transistor in the (a) off and (b) on configurations.

Image of FIG. 3.
FIG. 3.

relationship for spin transistors with channel lengths of (dashed line) 100 and (solid line) . Inset: Leakage current per device width.

Tables

Generic image for table
Table I.

Summary of the comparison between the spin transistor design of Ref. 8 and 2018 LSTP CMOS (Ref. 11).

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/content/aip/journal/apl/88/16/10.1063/1.2192152
2006-04-18
2014-04-21
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Performance of a spin-based insulated gate field effect transistor
http://aip.metastore.ingenta.com/content/aip/journal/apl/88/16/10.1063/1.2192152
10.1063/1.2192152
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