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Schematic barriers used in (a) a MOSFET and (b) a spin-based FET. A MOSFET works by controlling the height of the barrier, with a barrier height and width largely determined by the desired on-off current ratio and leakage current. The spin-based FET considered here works by controlling the nature of the initial state moving past the barrier in (b); if the initial state is fully spin polarized the transistor is off, otherwise it is on.
Spin transistor in the (a) off and (b) on configurations.
relationship for spin transistors with channel lengths of (dashed line) 100 and (solid line) . Inset: Leakage current per device width.
Summary of the comparison between the spin transistor design of Ref. 8 and 2018 LSTP CMOS (Ref. 11).
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