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Low-voltage high-mobility pentacene thin-film transistors with polymer/high- oxide double gate dielectrics
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10.1063/1.2206555
/content/aip/journal/apl/88/24/10.1063/1.2206555
http://aip.metastore.ingenta.com/content/aip/journal/apl/88/24/10.1063/1.2206555
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Figures

Image of FIG. 1.
FIG. 1.

(Color online) (a) A schematic cross-sectional view of our pentacene-based TFTs (channel length, ; width, ). (b) Plots of and (inset) characteristics measured from diameter Au-dot/dielectric insulator/ITO structures. Chosen dielectrics were , PVP , and thin and thick double combinations ( and , respectively).

Image of FIG. 2.
FIG. 2.

(Color online) AFM images of (a) film deposited on ITO glass, (b) PVP layer coated on glass, (c) pentacene film deposited on the single layer, and (d) another pentacene film deposited on the double layer.

Image of FIG. 3.
FIG. 3.

Drain current-drain voltage curves obtained from our pentacene-based TFTs with (a) PVP and (b) PVP dielectric combinations.

Image of FIG. 4.
FIG. 4.

and plots obtained from our pentacene TFTs with PVP and PVP double dielectrics under a drain saturation condition .

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/content/aip/journal/apl/88/24/10.1063/1.2206555
2006-06-16
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Low-voltage high-mobility pentacene thin-film transistors with polymer/high-k oxide double gate dielectrics
http://aip.metastore.ingenta.com/content/aip/journal/apl/88/24/10.1063/1.2206555
10.1063/1.2206555
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