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(a) Schematic top view and cross-sectional view of the device. Three lower gates (LGS, LGC, LGD) are used to form tunnel barriers. (b) Top-view scanning electron microscope image of the device before the upper gate is formed. (c) Equivalent circuit of the device with tunnel barriers separately tuned by , and .
(Color) Electrical characteristics (device 1). (a) Conductance of a MOSFET at LGD as a function of at (the characteristics of the single barrier). (b) CB oscillation of the SET transistor consisting of the long island with two barriers at LGS and LGD (, and ). The inset shows the results when of each barrier is , and 20 nS. (c) CB oscillation of the long island as a function of the upper gate voltage at , and . (d) CB oscillation of the short island with tunnel barriers at LGC and LGD (, and ). The configurations of tunnel barriers are schematically shown in each figure.
(Color) The Coulomb diamonds in the contour plot of the drain current vs and (device 1, ). Contour lines are 20 pA steps from low (red) to high (violet) in the range between and 390 pA.
(Color) Evolution from a single island to split double islands for device 2. (a) Equivalent circuit. (b)–(e), contour plots of the drain current vs and , and , respectively). Each is depicted by the arrow in Fig. 2(b). Contour lines run from low (red, 0 A) to high (violet, 1.4 nA) with 10-pA steps.
The capacitances estimated from the CB oscillations for three identically patterned devices. The three possible configurations forming a single charge island are described: a long island (barriers formed by LGS and LGD), a short island (two barriers by LGS and LGC), and a short island (two barriers by LGC and LGD).
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