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(a) Schematics of our transistor (cross section along the drain-source axis) with the gate (G), source (S), and drain (D). (b) Transmission electron microscope image of a device, corresponding to (a). (c) Electrostatic equivalent circuit. The tunnel barriers under the spacers replace the tunnel oxide junctions (boxes) of metallic SETs, and the transistor gate replaces the usual electrostatic capacitor. (d) Top view of the device showing the nanowire that is heavily doped except under the spacers (gray areas: tunnel barriers) and under the gate (black area: Coulomb island).
Linear drain-source conductance vs gate voltage in a , device with at various temperatures. Very small drain-source voltages are necessary at low temperature to stay in the linear regime: is at , at 100 and , and at . Inset: zoom on periodic Coulomb oscillations in linear scale.
Period of the oscillations in gate voltage in a device with , and , measured down to with a drain-source voltage of . The gate capacitance is independent of gate voltage. 115 peaks are recorded in the gate voltage range of , yielding a mean spacing and . Inset: calculated period from the geometry of 26 devices (with different widths, lengths, and gate oxide thickness) compared to measurements. The good agreement shows that the period is set by the MOS gate capacitance.
Top: Coulomb diamonds in a device with , , and . The slopes allow to determine the source and drain capacitances and . Bottom: numerical simulations of the doping (left) and potential (right) along the wire, deep below the interface, for a gate. The undoped regions below spacers and gate create a flattop potential that is lowered in its center by the gate voltage, creating a well isolated by two barriers.
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