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stacks for scaled-down memory devices: Effects of interfaces and thermal annealing
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10.1063/1.2360197
/content/aip/journal/apl/89/15/10.1063/1.2360197
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/15/10.1063/1.2360197
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Figures

Image of FIG. 1.
FIG. 1.

characteristics of the -type samples annealed in different gas environments. Similar effects were observed for the -type stacks. An insert shows the EOT of the -type stacks as a function of thickness (150 and ) in the samples as deposited and annealed at in the mixture. The extrapolation to a zero thickness of yields the effective EOT of the ON bilayer. A small increase of the bilayer EOT after annealing is observed.

Image of FIG. 2.
FIG. 2.

characteristics of -type samples (Au electrode): as grown and annealed at in , , and mixture. curve for the -type sample with the Pt electrode annealed at in is shown for comparison (Pt electrode is advantageous for blocking of electron injection at high currents).

Image of FIG. 3.
FIG. 3.

HRTEM images of samples [(a) and (b)] and [(c) and (d)] before [(a) and (c)] and after [(b) and (d)] annealing at in . Crystallization of and the evolution of the SiON interfacial layer are observed.

Image of FIG. 4.
FIG. 4.

Spatially resolved EELS spectra containing the and edges and recorded from the different layers in the -type stack annealed at in . The spectra reveal clear changes in the near-edge structure of the edge on going from -like to the amorphous interfacial layer. These changes are consistent with Al being present in the amorphous interfacial layer.

Image of FIG. 5.
FIG. 5.

(Color online) Charge loss effects observed in electron/hole-programmed capacitors (samples and annealed in ). (a) curves for the -type stacks with Au electrode: (1) initial; [(2) and (3)] programmed and biased positively and negatively, respectively, prior to the bake; and [(4) and (5)] biased positively and negatively, respectively, after bake. (b) curves for the - and -type stacks with Pt electrode: (1) -type initial; [(2) and (3)] -type programmed and biased positively and negatively, respectively, prior to the bake; [(4) and (5)] -type biased positively and negatively, respectively, after the bake; and [(6) and (7)] -type programmed prior to and after the bake, respectively (program window , ).

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/content/aip/journal/apl/89/15/10.1063/1.2360197
2006-10-12
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: SiO2∕Si3N4∕Al2O3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/15/10.1063/1.2360197
10.1063/1.2360197
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