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Logic gates with a single Hall bar heterostructure
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10.1063/1.2362989
/content/aip/journal/apl/89/15/10.1063/1.2362989
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/15/10.1063/1.2362989
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Four-terminal Hall bar configuration. (a) The gate is isolated from the bar and it is patterned between two voltage probes, denoted by source and drain . Resistances between the voltage probes and bar ends are denoted by and . (b) A two-input logic gate is obtained by replacing the voltage source with two digital voltage inputs and and series resistors .

Image of FIG. 2.
FIG. 2.

Measured longitudinal voltage on a Hall bar as a function of the bias at gate potential . Operating points which correspond to different logic functions are marked by symbols. XOR gate (circles) is obtained for and , NAND gate (squares) for and , NOR gate (triangles) for and , and NOT gate (rhombuses) for and . Inset: truth table of all presented gates. Logic levels and correspond to digital inputs shown in Fig. 1(b) .

Image of FIG. 3.
FIG. 3.

Digital wave forms measured on a Hall bar with input voltage levels chosen as in Fig. 2 .

Image of FIG. 4.
FIG. 4.

Output voltage of the NOT gate at input frequencies of , , and .

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/content/aip/journal/apl/89/15/10.1063/1.2362989
2006-10-13
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Logic gates with a single Hall bar heterostructure
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/15/10.1063/1.2362989
10.1063/1.2362989
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