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Nanowire-based multiple quantum dot memory
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View: Figures


Image of FIG. 1.
FIG. 1.

(Color online) (a) Schematic of the NW heterostructure design; white regions correspond to InAs, gray/black to InP. (b) Dark-field scanning-transmission electron microscope image of an long InP barrier recorded at the section marked in (a). (c) A one-dimensional array of long InAs QDs separated by thick InP barriers. (d) Schematic of the conduction band offsets. Electrons exist in the InAs conduction band on either side of the thick InP barrier. (e) In the QD wire, the Fermi level pinning leads to filling of the first few QD states. (f) Scanning electron microscope image of two NWs processed into a memory/readout configuration.

Image of FIG. 2.
FIG. 2.

(Color online) (a) sweeps for a SB NW. The hysteresis region in the FET current is symmetric in and centered around . Maximum amount of stored charge on the floating gate at is attained by sweeping to (, ). (b) A plot of the temperature dependence for the hysteresis observed in the FET current. Pronounced hysteresis is observed up to around , whereas at room temperature the thermal energy is sufficient to excite carriers over the InP barrier. (c) sweeps for a QD NW. The hysteresis region in the FET current is displaced to positive due to QD states near the Fermi level (, ). (d) A similar behavior as in (b) is observed for the QD wire. In this case the hysteresis disappears at around .

Image of FIG. 3.
FIG. 3.

Change in FET current is measured after reset and write pulses, respectively. The length of the set pulse is reduced from (, ). (a) The SB memory is successfully charged for write pulses with lengths . (b) The QD memory is successfully charged for write pulses with lengths .


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Scitation: Nanowire-based multiple quantum dot memory