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Spatial and energetic distribution of border traps in the dual-layer high- gate stack by low-frequency capacitance-voltage measurement
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10.1063/1.2364064
/content/aip/journal/apl/89/16/10.1063/1.2364064
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/16/10.1063/1.2364064
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Capacitance-voltage curves of the MOS capacitor at various frequencies. The capacitance increase at lower frequencies could be explained by proposing a frequency- and voltage-dependent border trap capacitance in parallel with the ideal dielectric capacitance as shown in the inset.

Image of FIG. 2.
FIG. 2.

Border trap capacitance as a function of measurement frequency at various gate bias voltages. The inset shows that the is linearly proportional to the gate area as proposed.

Image of FIG. 3.
FIG. 3.

Schematic band diagram of the MOS capacitor biased in the accumulation region with the illustrations of tunneling distance and carrier energy coordinates.

Image of FIG. 4.
FIG. 4.

Spatial and energetic distribution of the border trap volume density in the dual-layer high- gate stack. Symbols are model-extracted data points, and 3D mesh is the smoothed surface profiling of these points.

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/content/aip/journal/apl/89/16/10.1063/1.2364064
2006-10-20
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/16/10.1063/1.2364064
10.1063/1.2364064
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