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Capacitance-voltage curves of the MOS capacitor at various frequencies. The capacitance increase at lower frequencies could be explained by proposing a frequency- and voltage-dependent border trap capacitance in parallel with the ideal dielectric capacitance as shown in the inset.
Border trap capacitance as a function of measurement frequency at various gate bias voltages. The inset shows that the is linearly proportional to the gate area as proposed.
Schematic band diagram of the MOS capacitor biased in the accumulation region with the illustrations of tunneling distance and carrier energy coordinates.
Spatial and energetic distribution of the border trap volume density in the dual-layer high- gate stack. Symbols are model-extracted data points, and 3D mesh is the smoothed surface profiling of these points.
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