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Device scaling in sub- pentacene field-effect transistors
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10.1063/1.2364154
/content/aip/journal/apl/89/18/10.1063/1.2364154
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/18/10.1063/1.2364154
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Scanning electron microscopy (SEM) image of a set of pentacene field-effect transistors (top view). The top inset is a schematic cross section (not drawn to scale) of a single FET. The bottom inset is a SEM image of a channel length device showing a single grain of pentacene spanning the gap.

Image of FIG. 2.
FIG. 2.

Plot of vs and (inset) plot of vs ( scanned from to and scanned from to ) for (a) a channel length pentacene FET with a gate dielectric and (b) a channel length pentacene FET with a gate dielectric. (c) Plot of vs ( scanned from to ) for of (closed circle), (open circle), and (closed triangle).

Image of FIG. 3.
FIG. 3.

(a) Plot of field-effect differential conductance vs channel length for pentacene organic FETs with (dark circles), (open circles), and (dark triangles) gate oxide thicknesses. Differential conductances are calculated from characteristics where is scanned from at for the gate oxide, is scanned from at for the gate oxide, and is scanned from at for the gate oxide. (b) Plot of the normalized contact resistance vs for thicknesses of 3, 5, and . Device resistances are calculated in the linear regime from the slope of the characteristics where both and are scanned from for the gate oxide, for the gate oxide, and for the gate oxide.

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/content/aip/journal/apl/89/18/10.1063/1.2364154
2006-10-30
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Device scaling in sub-100nm pentacene field-effect transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/18/10.1063/1.2364154
10.1063/1.2364154
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