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Low-voltage and high-gain pentacene inverters with plasma-enhanced atomic-layer-deposited gate dielectrics
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10.1063/1.2234835
/content/aip/journal/apl/89/3/10.1063/1.2234835
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/3/10.1063/1.2234835
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) The transfer characteristics of the pentacene transistor and (b) the voltage transfer characteristics of the D inverter with an gate dielectric. The insets of (a) and (b) show the drain current-voltage characteristics of the driver transistor as a function of the gate voltage and a schematic of D inverter, respectively.

Image of FIG. 2.
FIG. 2.

(a) The transfer characteristics of the pentacene transistor and (b) the voltage transfer characteristics of the D inverter with a gate dielectric.

Image of FIG. 3.
FIG. 3.

Hysteresis behavior of the voltage transfer characteristics with (a) the change of the range at and (b) the change of at input voltages ranging from .

Image of FIG. 4.
FIG. 4.

Hysteresis behavior of the transfer characteristics of the driver transistor under when was swept from and back to , from and back to , and finally from and back to .

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/content/aip/journal/apl/89/3/10.1063/1.2234835
2006-07-21
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Low-voltage and high-gain pentacene inverters with plasma-enhanced atomic-layer-deposited gate dielectrics
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/3/10.1063/1.2234835
10.1063/1.2234835
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