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Interference of charge carrier in a double-dot nanopillar transistor
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Image of FIG. 1.
FIG. 1.

(a) Schematic drawing of the double-dot nanopillar transistor. The overall structure is . A side gate is arranged at a close distance of to the dots. (b) Scanning electron microscope picture of the device after completion.

Image of FIG. 2.
FIG. 2.

Drain current as a function of drain-source voltage for fixed ranging from , in step of . The inset shows an expanded view of the beats at low bias for .

Image of FIG. 3.
FIG. 3.

(a) Dependence of drain current vs positive gate voltages of 0, 0.02, and , respectively. (b) Data at negative bias. Notice that at large bias of , periodical peaks are disrupted, which is an indication of strong interference between the gate-source (transverse) modes and the drain-source (longitudinal) modes as described in Ref. 6.


Generic image for table
Table I.

Theoretical capacitance and charging energy of each layer material in the transistor. For and , the parameters used in the calculations are , , , and . For , equals ; for , ; for , and ; for , and . Note that and are the easy spots for excitation.

Generic image for table
Table II.

Quantum states and their energy levels of the central dot as derived from Eq. (1). The active size in the modeling is . The first excited state is [1,1,1]. Next excited state is [2,2,2] which is expected to have a uniform charge excitation. The first triplet states correspond to the lower threshold at as seen in Fig. 3(a). The next triplet states correspond to another threshold observed at .


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Interference of charge carrier in a double-dot nanopillar transistor