banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Electrostatically gated Si devices: Coulomb blockade and barrier capacitance
Rent this article for
View: Figures


Image of FIG. 1.
FIG. 1.

(Color online) Left side: schematic representation of the device as fabricated. The Si wire runs between two pads which are heavily doped outside the region covered by the upper gate. Right:circuit diagram representing the effect of the three lower gates LG-S, LG-C, and LG-D, but not the upper gate. The two outside lower gates form the tunnel junctions; the middle lower gate is used to modulate the potential of the island and therefore forms the capacitive gate to this transistor.

Image of FIG. 2.
FIG. 2.

Measurement of conduction through a single barrier. With the other upper and lower gates set to be conducting, this shows the dependence of the conductance of the single barrier due to the gate closest to the drain. The applied bias voltage and we measure the bias current . . This curve shows the standard features for a MOSFET: exponential subthreshold dependence and linear dependence above threshold; the threshold voltage is approximately . We have subtracted a parasitic resistance of .

Image of FIG. 3.
FIG. 3.

(Color online) Measurement of SET oscillations for the same device as in Fig. 2. Here, the device is operating as a SET transistor, with the two outside lower gates set to have approximately the same conductance. The five curves shown have a range of conductances from approximately . The voltage applied to the drain gate is as indicated; we know that from Fig. 2, the threshold voltage for conduction of this gate is approximately . The horizontal line represents the conductance quantum for two junctions in series, . Note that the SET oscillations are reduced in size by a large factor at conductances well below the quantum value. .

Image of FIG. 4.
FIG. 4.

(Color online) Inset: “diamond diagram” to obtain barrier capacitance. This figure is for a second device, different from the device shown in the previous two figures. The range of was over slightly less negative voltages than in the previous two figures. By interpolating a large number of curves of the type shown in Fig. 3 at different bias voltages , we can obtain the dependence of the bias voltage on the gate voltage at fixed current . The curves are offset vertically for clarity, by 0.7 and . From bottom to top, the values of are , , , corresponding to drain barrier conductances of , , and . Lines are straight line fits to the negative slopes. Main: the barrier capacitance for the drain barrier versus the gate voltage for the drain barrier. These data are derived from the slopes of the lines as shown in the inset and other curves not shown. . The error bars come from the numerical uncertainty in the fitting of the slope. As described in the text, these Coulomb blockade measurements appear to be the only way to measure this effective “barrier capacitance” due to an electrostatically produced barrier.


Article metrics loading...


Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Electrostatically gated Si devices: Coulomb blockade and barrier capacitance