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Probing nanoscale local lattice strains in advanced Si complementary metal-oxide-semiconductor devices
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10.1063/1.2336085
/content/aip/journal/apl/89/6/10.1063/1.2336085
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/6/10.1063/1.2336085
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Figures

Image of FIG. 1.
FIG. 1.

(Color online) (a) Schematic diagram of a Si PMOS transistor with SiGe layers in the source and drain regions. A one-dimensional strain map is obtained by acquiring the CBED patterns from the spots marked in the image, where the compressive strain gradient in the direction is measured. (b) The ⟨340⟩ ZA CBED pattern (contrast reversed for easy comparison) superimposed by the kinematically simulated one is taken from a position that is away from the gate-channel interface. The compressive strain tensors are determined to be , , and .

Image of FIG. 2.
FIG. 2.

(a) Cross-sectional TEM image of a Si NMOS transistor. (b) The experimental CBED pattern taken at the ⟨910⟩ ZA.

Image of FIG. 3.
FIG. 3.

(Color online) Tensile strain distributions in the (a) and (b) directions with a different silicon nitride capping layer thickness. is the distance from the position where the CBED pattern is taken to the gate-channel interface.

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/content/aip/journal/apl/89/6/10.1063/1.2336085
2006-08-09
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Probing nanoscale local lattice strains in advanced Si complementary metal-oxide-semiconductor devices
http://aip.metastore.ingenta.com/content/aip/journal/apl/89/6/10.1063/1.2336085
10.1063/1.2336085
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