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Wide temperature SETs process overview. (a) View of the trench in the oxide layer and its top down SEM picture including the intensity profile showing where the linewidth is measured. Below the oxide layer is the silicon substrate used as a back gate. (b) The island formation. The open end drawing of the perpendicular Ti line shows the layer grown on the future island. (c) The titanium blanket layer is deposited. (d) End result after CMP.
Electrical characterization at room temperature. (a) Asymmetrical SET data with at (◻) and at (엯). The inset shows a wider range (◻). The line represents the model calculations with , , , and . (b) Symmetrical SET data with tunnel junction dielectric thickness of for at (◻) and at (엯). The line represents the model calculation with , , , and .
SET drain current behavior as a function of the back-gate bias at low drain voltage . The line is the asymmetrical SET model and the squares (◻) are the data. A dotted line is added as a guide to the eye. A gate to source leakage to of was removed from the data to represent it on the same scale as the model.
SET curves as a function of temperature for the design with the charging energy of . Temperatures are (∎), (●), (▴), (▾), and (◆). The back gate is grounded except for the open circles where is at .
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