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Formation of stacked Ni silicide nanocrystals for nonvolatile memory application
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10.1063/1.2713177
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    Affiliations:
    1 Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan 300, Republic of China
    2 Department of Physics and Institute of Electro-Optical Engineering, Center for Nonoscience and Nanotechnology, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung, Taiwan 804, Republic of China
    3 Department of Photonics, National Chiao Tung University, Hsin-Chu, Taiwan 300, Republic of China and Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan 300, Republic of China
    4 Department of Physics, National Sun Yat-Sen University, Taiwan 804, Republic of China, and Institute of Electro-Optical Engineering, National Sun Yat-Sen University, Taiwan 804, Republic of China
    5 Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan 300, Republic of China
    a) Electronic mail: tcchang@mail.phys.nsysu.edu.tw
    Appl. Phys. Lett. 90, 112108 (2007); http://dx.doi.org/10.1063/1.2713177
/content/aip/journal/apl/90/11/10.1063/1.2713177
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/11/10.1063/1.2713177
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Figures

Image of FIG. 1.
FIG. 1.

Schematic of (a) as deposition for a silicon substrate/ /oxygen-incorporated structure, (b) deposited layer precipitated to Ni silicide nanocrystals and oxygen-incorporated layer oxidized to form the blocking oxide during the RTO process, and (c) stacked Ni silicide nanocrystals embedded in silicon oxide after RTO process at for . (d) Cross-sectional HRTEM analysis of stacked Ni silicide nanocrystals. The sizes of the nanocrystals (from substrate to blocking oxide) and density are and , respectively.

Image of FIG. 2.
FIG. 2.

Capacitance-voltage hysteresis of the MOIOS structure after the bidirectional voltage sweeps from and from .

Image of FIG. 3.
FIG. 3.

Charge retention characteristics of the stacked structure with Ni silicide nanocrystals.

Image of FIG. 4.
FIG. 4.

(a) Programming characteristics of nanocrystal memory device at different gate programming voltages. (b) Schematic band diagram of the MOIOS structure operated at low voltage (solid line) and high voltage (dash line).

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/content/aip/journal/apl/90/11/10.1063/1.2713177
2007-03-14
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Formation of stacked Ni silicide nanocrystals for nonvolatile memory application
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/11/10.1063/1.2713177
10.1063/1.2713177
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