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Schematic of (a) as deposition for a silicon substrate/ /oxygen-incorporated structure, (b) deposited layer precipitated to Ni silicide nanocrystals and oxygen-incorporated layer oxidized to form the blocking oxide during the RTO process, and (c) stacked Ni silicide nanocrystals embedded in silicon oxide after RTO process at for . (d) Cross-sectional HRTEM analysis of stacked Ni silicide nanocrystals. The sizes of the nanocrystals (from substrate to blocking oxide) and density are and , respectively.
Capacitance-voltage hysteresis of the MOIOS structure after the bidirectional voltage sweeps from and from .
Charge retention characteristics of the stacked structure with Ni silicide nanocrystals.
(a) Programming characteristics of nanocrystal memory device at different gate programming voltages. (b) Schematic band diagram of the MOIOS structure operated at low voltage (solid line) and high voltage (dash line).
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