No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Chip cooling with integrated carbon nanotube microfin architectures
1.A. Bar-Cohen and W. M. Rohsenow, ASME J. Heat Transfer 106, 116 (1984).
2.R. E. Simons, V. W. Antonetti, W. Nakayama, and S. Oktay, Heat Transfer in Electronic Packages in Microelectronics Packaging Handbook (Chapman and Hall, New York, 1997), Vol. 1, Chap. 4, p. 314.
3.D. Tuckerman and R. Pease, IEEE Electron Device Lett. 2, 126 (1981).
9.M. Zhimin, R. Morjan, J. Anderson, E. E. B. Campbell, and J. Liu, Proceedings of the IEEE 55th Electronic Components and Technology Conference, Lake Buena Vista, FL, 31 May 2005, pp. 51–54.
10.M. Zhimin, J. Anderson, and J. Liu, Proceedings of the IEEE 6th High Density Microsystem Design and Packaging and Component Failure Analysis Conference, Shanghai, China, 30 June 2004, pp. 373–376.
12.X. S. Li, A. Y. Cao, Y. J. Yung, R. Vajtai, and P. M. Ajayan, Nano Lett. 5, 1997 (2005).
13.S. Talapatra, S. Kar, S. K. Pal, R. Vajtai, L. Ci, P. Victor, M. M. Shaijumon, S. Kaur, O. Nalamasu, and P. M. Ajayan, Nature Nanotechnology 1, 112 (2006).
See EPAPS Document No. for the consecutive steps of device fabrication; soldering the flip chip onto the substrate; usage of solder flux; and finally a block of aligned nanotube structure along its Cr/Cu sputtered side was positioned and soldered on the chip by a fine-placer. This document can be reached via a direct link in the online article’s HTML reference section or via the EPAPS homepage (http://www.aip.org/pubservs/epap.html
16.L. A. Brignoni and S. V. Garimella, IEEE Trans. Compon., Packag. Manuf. Technol., Part A 22, 399 (1999).
18.S. T. Huxtable, D. G. Cahill, S. Shenogin, L. R. Ozisik, P. Barone, M. Usrey, M. S. Strano, G. Siddons, M. Shim, and P. Keblinski, Nat. Mater. 2, 731 (2003).
19.J. G. Maveety and H. H. Jung, IEEE Trans. Compon. Packag. Technol. 25, 459 (2002).
Article metrics loading...
Efficient cooling of silicon chips using microfin structures made of aligned multiwalled carbon nanotube arrays is achieved. The tiny cooling elements mounted on the back side of the chips enable power dissipation from the heated chips on the level of modern electronics demands. The nanotube fins are mechanically superior compared to other materials being ten times lighter, flexible, and stiff at the same time. These properties accompanied with the relative simplicity of the fabrication makes the nanotubestructures strong candidates for future on-chip thermal management applications.
Full text loading...
Most read this month