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Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained -channel metal-oxide-semiconductor field-effect transistors with SiN capping
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10.1063/1.2715122
/content/aip/journal/apl/90/12/10.1063/1.2715122
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/12/10.1063/1.2715122
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Percentage increase of transconductance vs channel length for different splits of samples with respect to the control ones. Each datum point represents the mean measurement value from six devices. Inset: capacitance-voltage characteristics for all splits. Basically all curves are identical, indicating the transconductance increase is not caused by the oxide thickness difference among all splits.

Image of FIG. 2.
FIG. 2.

(Color online) Substrate current vs gate voltage for different splits with channel width/length of .

Image of FIG. 3.
FIG. 3.

(Color online) shift as a function of stress time. Devices with channel width/length of were stressed at , and of maximum substrate current. Each datum point represents the mean measurement value from three devices.

Image of FIG. 4.
FIG. 4.

(Color online) (a) In SiN-capped devices, a large amount of hydrogen species from the SiN layer diffuse to the gate oxide layer and the channel region through three possible pathways denoted as A1, A2, and A3. (b) In BL-POLY devices, the diffusion of hydrogen species from SiN is suppressed by the poly-Si buffer layer.

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/content/aip/journal/apl/90/12/10.1063/1.2715122
2007-03-20
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal-oxide-semiconductor field-effect transistors with SiN capping
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/12/10.1063/1.2715122
10.1063/1.2715122
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