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Thermal annealing effects on the electrical characteristics of the back interface in nano-silicon-on-insulator channel
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10.1063/1.2719641
/content/aip/journal/apl/90/14/10.1063/1.2719641
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/14/10.1063/1.2719641
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic diagram of metal-point-contact FET (a) and normal SOI MOSFET (b) devices fabricated on the SOI substrate.

Image of FIG. 2.
FIG. 2.

characteristics and characteristics (inset) for metal-point-contact FET.

Image of FIG. 3.
FIG. 3.

characteristics as a function of RTA temperature (a) and the back interface-state distributions (b).

Image of FIG. 4.
FIG. 4.

characteristics as a function of furnace annealing temperature after RTA (a) and back interface-state distributions (b).

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/content/aip/journal/apl/90/14/10.1063/1.2719641
2007-04-04
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Thermal annealing effects on the electrical characteristics of the back interface in nano-silicon-on-insulator channel
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/14/10.1063/1.2719641
10.1063/1.2719641
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