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Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization
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10.1063/1.2748366
/content/aip/journal/apl/90/26/10.1063/1.2748366
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/26/10.1063/1.2748366
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic of (a) a single-gate (SG) TFET device and (b) a double-gate (DG) TFET device. (c) Extracted energy band diagram for DG TFET along the source-to-channel direction at the surface based on 2D numerical device simulation, illustrating the modulation of the tunneling barrier width from the off state to the on state.

Image of FIG. 2.
FIG. 2.

(a) Comparison of the gate characteristics between SG TFET and DG TFET devices, clearly showing the advantage of employing a double-gate structure. Excellent subthreshold swing is achieved with times on-state current enhancement for the DG TFET device. (b) Plot of on-state drain current and average current density as a function of silicon film thickness . The device operation spans from the regime of volume limitation to that of single-gate control limitation.

Image of FIG. 3.
FIG. 3.

(a) Electric potential extracted along the direction near the band-to-band tunneling region of the source-channel interface. (b) Tunneling barrier width extracted near the surface and the center of the film for various silicon thicknesses.

Image of FIG. 4.
FIG. 4.

(a) Plot of band-to-band tunneling rate along the direction near the source-channel region. (b) Integration of along the direction showing the optimal point for maximum tunneling current.

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/content/aip/journal/apl/90/26/10.1063/1.2748366
2007-06-27
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/26/10.1063/1.2748366
10.1063/1.2748366
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