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Two-dimensional analysis for emitter ledge thickness of heterojunction bipolar transistors
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10.1063/1.2432224
/content/aip/journal/apl/90/4/10.1063/1.2432224
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/4/10.1063/1.2432224
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic cross section of a simulated device.

Image of FIG. 2.
FIG. 2.

Distributions of recombination rate of the studied devices (without any passivation) and (with thickness emitter ledge passivation). The biased voltages are fixed at and .

Image of FIG. 3.
FIG. 3.

Electron densities along the cutline of the studied devices with different emitter ledge thicknesses. The biased voltages are fixed at and . The corresponding hole densities are also revealed in the inset.

Image of FIG. 4.
FIG. 4.

Relationships between the dc current gain and emitter ledge thickness for simulated and experimental devices.

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/content/aip/journal/apl/90/4/10.1063/1.2432224
2007-01-25
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Two-dimensional analysis for emitter ledge thickness of InGaP∕GaAs heterojunction bipolar transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/90/4/10.1063/1.2432224
10.1063/1.2432224
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