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(a) TEM image of an nanowire grown on substrate using gold nanoparticles as catalyst. Top left inset shows the nanowire crystalline lattice structure and bottom right inset shows the SAED pattern. (b) Top view of the fabricated nanowire memory device. Pt interconnection lines were deposited by focused ion beam, linking the nanowire with prepatterned Mo probing pads.
Resistance of nanowire memory (measured at a small read voltage of ) as a function of applied voltage in a pulse-mode test. (a) Switching from low-resistance state to high-resistance state with a fixed pulse width of . The reset starts to occur at . (b) Switching from high-resistance state to low-resistance state with a fixed pulse width of . The set starts to occur at .
(a) Measured characteristics and (b) characteristics of nanowire memory, both plots showing four successive testing sweeps after nanowire was either set to low-resistance state or reset to high-resistance state.
Measured nanowire device resistance for a series of high and low resistance states after repeated reset-set programing cycles. Device was switched from LRS to HRS using a reset pulse (with sharp fall-down edge), and from HRS to LRS using a set pulse.
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