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(Color online) Schematic illustration of the device fabrication process.
(Color online) (a) Co oxide NC array after the removal of the PS--PVP micelles loaded with deposited on the -coated Si substrate by plasma treatment. (b) Metallic Co NC array reduced by annealing. (c) The Co binding energy region acquired from the loaded micelles after their exposure to an plasma and subsequent annealing. The binding energy change indicates that the Co oxide NCs were reduced to metallic Co NCs.
(Color online) (a) responses of the memory devices after the application of program/erase bias pulses. Different types of devices were fabricated and compared according to the reduction nature of the charge trap layers with Co oxide NCs and metallic Co NCs used as charge trap elements, respectively. (b) Time dependence of data retention properties for programed and erased states.
(Color online) Nanoscale measurement of nonvolatile memory characteristics. (a) Two-dimensional SNDM image with clearly distinguishable programed and erased states. (b) Three-dimensional SNDM image whose area corresponds to the image shown in (a).
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