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Tilted SEM view of porous stack (left) after the etching of the TiN and (right) after the etching of the porous SiOCH.
SEM top view of arrays of dielectric ridges (: 100, 75, 60, ). Left-hand side: porous SiOCH with a ridge height of ; middle: porous SiOCH with ridge height of ; right-hand side: dense SiOCH with an etched depth of . Undulations are observed for widths (respectively ) with a height of (respectively ) of porous SiOCH ridges and for widths with a height of of dense SiOCH ridges.
Evolution of buckling coefficient calculated from the simulation for different height and width of ridges with a porous SiOCH (line) and a dense SiOCH (dots). A Buckling coefficient lower than unity leads to a buckled structure.
Map of buckling coefficient thresholds as a function of dielectric Young modulus and mask residual stress plotted for the geometrical dimensions corresponding to ridges dimensions of the next integrated circuits integrated in 2010, 2013, 2016, and 2019. Each curve shown in this graph corresponds to a buckling coefficient of 1 and separates the residual stress/Young modulus plan into two areas. For each generation of integrated circuits, the left part of the plan delimitated by the curve corresponds to a buckling coefficient lower than 1 (wiggling), while the right part corresponds to a buckling coefficient higher than 1 (no wiggling).
Mechanical properties and residual stress of materials used in our structure.
Geometrical dimensions recommended by the 2006 International Technological Roadmap for Semicontuctor (ITRS) industry for the first level of metal in microprocessor units. Those generations of integrated circuits are supposed to be integrated in 2010, 2013, 2016, and 2019 (Ref. 14).
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