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(Color online) (a) Scanning electron microscopy image of a side-gated FET. The in situ doped polycrystalline silicon side gates are isolated from the single-crystal Si (sc-Si) active area by a thin layer of . Thermally grown isolates the top gate from the active area and the side gates. (b) Cross-section schematics along the width of the device. Current flow is at the top interface in and out of plane. STI is composed of and low stress silicon nitride. . (c) three-dimensional schematics of the device structure.
(Color online) Electrical characteristics of an ultranarrow channel device. Estimated channel width is . (a) Transfer characteristics for and and (red) and (black). Subthreshold behavior indicates charge trapping and detrapping events at the side silicon–silicon nitride interfaces. Drain induced barrier lowering (DIBL) is very small. (b) Output characteristics for and and steps.
(Color online) (a) Threshold voltage response to , extracted using constant current method in subthreshold regime and linear interpolation in the “on” regime. (b) graphed as a function of square root of .
(Color online) Cross-section schematic illustrating accumulated body operation. Holes are drawn from the substrate, connected to ground, into the device body. is the depletion depth under the top gate for a wide device. In the ultranarrow channel device is reduced to due to accumulation of the body with holes when a large negative is applied.
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