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Typical capacitance-voltage hysteresis characteristics of the memory devices with and without the BONs were obtained. The sweep loops included , , and . The inset figure examines the flatband voltage shift as function of the various sweep loops.
Morphology and the composition of the BONs were detected by the (a) SEM and (b) EDS of the TEM, respectively. The cross section of the structure was shown in the inset of figure (b). In order to prevent the BONs peeling off the HfON surface, the capping layer was used. Then, the cross section sample was prepared by the focus ion beam. The peaks of the Si, Pd, and Pt were detected due to the capping layer.
(a) Band diagrams of the electron and hole injection operation using and , respectively, biased at the control gate of the MOS devices with the BONs embedded in the HfON high- gate dielectric were shown. (b) Programing properties of the MOS devices with the BONs under various programing times by and , respectively, were shown.
Charge retention properties of the MOS devices with the BONs using programing voltages performed at room temperature were shown.
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