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(a) Conventional nTFET (highly-doped -type source region, intrinsic channel region, highly-doped -type drain region) with flexible gate structure: the dashed line shows the conventional gate structure, the filled box represents a shortened gate. (b) Cross-section of the most straightforward implementation of a vertical nanowire-based FET (TFET or MOSFET depending on the source doping type). Starting from a substrate, a highly-doped drain region is formed. Then a nanowire is fabricated after which a low- dielectric is deposited to reduce gate-drain capacitance. The nanowire is then covered with a gate dielectric and a gate electrode. After etching free the top of the nanowire again, a nanowire top implantation is done which forms the source region. Finally, source, drain, and gate electrodes are fabricated.
(Color online) Simulated dc output characteristics of all-silicon FETs. Source and drain doping: ; channel doping: -type, ; gate dielectric: hafnium oxide, thick; source-gate (when applicable: gate-drain) overlap: ; . (a) TFETs with short and full (110 or ) gate. The inset shows the intrinsic transient behavior for (at time , a voltage source of is applied to the gate, while the gate current is limited to at by the presence of a series resistance; implies that all TFETs have identical dc performance; ): the charging of the SG-TFETs is equally fast and faster than the charging of the corresponding full-gate TFETs by factors of approximately and , respectively. (b) FETs with channel length: , .
(Color online) Simulated dc output characteristics of an all-germanium TFET (germanium has a small band gap and therefore a large tunnel probability which makes the ambipolar behavior more pronounced). Source and drain doping: ; channel doping: -type, ; gate dielectric: hafnium oxide, thick; source-gate (when applicable: gate-drain) overlap: ; “shorter gate” curve: gate-drain separation of ; . Reduction of the total gate length with reduces the off-current with three to five orders of magnitude.
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