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Control of full width at half maximum of Coulomb oscillation in silicon single-hole transistors at room temperature
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10.1063/1.2767765
/content/aip/journal/apl/91/5/10.1063/1.2767765
http://aip.metastore.ingenta.com/content/aip/journal/apl/91/5/10.1063/1.2767765
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Cross-sectional view of SCT. (a) Substrate depletion mode. (b) Substrate accumulation/inversion mode. is varied by changing the substrate condition.

Image of FIG. 2.
FIG. 2.

(Color online) (a) Measured characteristics of SHT-A for various at RT. is . (b) dependence of . (c) Coulomb diagram of SHT-A at RT. Slopes guided with lines are used to calculate the capacitance ratios at the first peak. At higher , slopes decrease and the diamond gets squeezed due to the source/drain capacitance increase by lowering the tunneling barrier. (d) and FWHM of the first CB peak as a function of .

Image of FIG. 3.
FIG. 3.

(Color online) (a) Measured characteristics of SHT-B for various at . is . (b) dependence of . (c) Coulomb diagram of SHT-B at . Compared to Fig. 2(c), there is no degradation in CB diamond. (d) and FWHM of the second CB peak as a function of .

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/content/aip/journal/apl/91/5/10.1063/1.2767765
2007-08-02
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Control of full width at half maximum of Coulomb oscillation in silicon single-hole transistors at room temperature
http://aip.metastore.ingenta.com/content/aip/journal/apl/91/5/10.1063/1.2767765
10.1063/1.2767765
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