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Lifetime modeling for stress-induced voiding in integrated circuit interconnections
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10.1063/1.2766695
/content/aip/journal/apl/91/6/10.1063/1.2766695
http://aip.metastore.ingenta.com/content/aip/journal/apl/91/6/10.1063/1.2766695
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic of an initial defect located at the cross section of grain boundary and passivation layer at the line edge. (b) Experimental result of a void formed due to thermomechanical stress.

Image of FIG. 2.
FIG. 2.

Three cases of stress relaxation volume evolution indicated by the gray area. The relationship between the stress relaxation volume and the diffusion length is categorized as (a) linear, (b) square, and (c) cubic.

Image of FIG. 3.
FIG. 3.

Critical temperature profile as a function of activation energy and temperature exponent. Stress free temperature is set at .

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/content/aip/journal/apl/91/6/10.1063/1.2766695
2007-08-06
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Lifetime modeling for stress-induced voiding in integrated circuit interconnections
http://aip.metastore.ingenta.com/content/aip/journal/apl/91/6/10.1063/1.2766695
10.1063/1.2766695
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