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(a) Evolution of for a -MOSFET during PBD. The -MOSFET was stressed using a two-stage CVS in inversion mode at the room temperature. and were used in the first-stage CVS. In the second-stage CVS, the -MOSFET was stressed with without setting any limit on . (b) Post-BD characteristics of the -MOSFET in stages I, II, and III, which were measured in accumulation mode. is the substrate current.
(a) Typical example for the TEM image of a BD -MOSFET with the presence of DBIE in stages II and III. It is believed that the percolation path is situated on top of DBIE. (b) General schematic showing the postulated field-emission (i.e., the -poly-Si gate/percolation path contact) and thermionic-emission barrier (i.e., the percolation path/ substrate contact) in the vicinity of the percolation path.
(a) Evolution of the ideality factors for a -MOSFET during PBD. and are the ideality factors extracted from the post-BD and curves in accumulation mode, respectively. (b) Evolution of for six -MOSFETs with different initial during PBD, showing that are generally independent on .
Evolution of for a -MOSFET in stages I, II, and III. are the slopes of the vs (1/kT) relationship, which can be obtained from Eq. (2) for lower than . The post-BD characteristics at a specific instant of PBD were measured at 298, 313, 333, and , as shown in the inset. in stages I and II with are also included for comparison.
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