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Hysteresis mechanisms of pentacene thin-film transistors with polymer/oxide bilayer gate dielectrics
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FIG. 1.

(a) Illustration of hysteresis mechanisms: (1) channel/dielectric interface-induced, (2) slow polarization-induced, and (3) gate charge injection-induced hystereses. (b) A schematic cross-sectional view of our pentacene-based TFTs (channel length , width ).

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FIG. 2.

and plots obtained under (linear regime) from our pentacene TFTs with PVP bilayers prepared under two different PVP curing time conditions: (a) and (b) at (vacuum). Similar plots also obtained under (linear regime) from our pentacene TFTs with PVP bilayers prepared with (c) and (d) curing.

Image of FIG. 3.

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FIG. 3.

Fourier transformation infrared (FTIR) spectra of thick and thin PVP layers to examine the existence of OH groups.

Image of FIG. 4.

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FIG. 4.

and plots obtained from our pentacene TFT with cured thin PVP/ thick bilayer under (linear regime).

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2008-01-07
2014-04-23

Abstract

We have studied the electrical stability of organic poly-4-vinyl phenol (PVP)/inorganic oxide bilayer gate dielectrics for low-voltage pentacene thin-film transistors(TFTs). Curing conditions of spin-cast PVP influence on the drain current-gate bias hysteresis behavior; long term curing reduces the magnitude of the hysteresis, which can also be reduced by decreasing the PVP thickness. The electron charge injection from gate electrode plays as another cause of the electrical hysteresis. These instabilities are categorized into the following three: channel/dielectric interface-induced, slow polarization-induced, and gate charge injection-induced hystereses. By examining the hysteresis behavior of pentacene TFTs with five different combinations of bilayer dielectric, we clarified the instability mechanisms responsible for the electrical hysteresis.

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Scitation: Hysteresis mechanisms of pentacene thin-film transistors with polymer/oxide bilayer gate dielectrics
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/1/10.1063/1.2830329
10.1063/1.2830329
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